1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device equipped with a DLL (delay-locked loop) circuit.
2. Description of the Related Art
Some semiconductor devices control a timing of a clock signal by use of a DLL circuit or the like.
FIG. 1 is a block diagram of a configuration in which a DLL circuit is used as a timing-stabilization circuit for data-output operations.
The configuration of FIG. 1 includes an input circuit 501, a variable-delay circuit 502, a clock-control circuit 503, a signal-line delay 504, an output circuit 505, a frequency divider 506, a phase comparator 507, a delay-control circuit 508, a variable-delay circuit 509, a dummy-clock-control circuit 510, a dummy-signal-line delay 511, a dummy-output circuit 512, a dummy-load circuit 513, a dummy-input circuit 514, and an overflow detector 515.
A clock signal CLK input to the input circuit 501 is compared with a reference voltage, and is supplied from the input circuit 501 as an internal-clock signal i-clk. The internal-clock signal i-clk is delayed by the variable-delay circuit 502 by an appropriate delay amount, and is supplied to the output circuit 505 via the clock-control circuit 503 and the signal-line delay 504. The output circuit 505 uses the internal-clock signal i-clk having the appropriate delay amount as a synchronization signal so as to latch data DATA. The latched data DATA is then supplied from the output circuit 505 to an exterior of the semiconductor device as data DQ.
The signal path from the input point of the clock signal CLK to the output circuit 505 inevitably introduces a delay which is inherent to the circuit, so that the data DATA output from the output circuit 505 to the exterior of the device has a timing displacement relative to the clock signal CLK. In order to ensure that the data DATA output from the output circuit 505 to the exterior of the device is adjusted to have a predetermined timing relation with the externally provided clock signal CLK, a DLL circuit mainly comprised of the phase comparator 507, the delay-control circuit 508, and the variable-delay circuit 509 is employed.
The internal-clock signal i-clk is subjected to frequency division in the frequency divider 506 to generate a dummy-clock signal d-clk and a reference-clock signal c-clk. The dummy-clock signal d-clk having the same phase as the internal-clock signal i-clk is supplied to the variable-delay circuit 509. The variable-delay circuit 509 is controlled to delay the dummy-clock signal d-clk by the same delay amount as that applied by the variable-delay circuit 502. A delayed-dummy-clock signal d-dll-clk output from the variable-delay circuit 509 is then supplied to the dummy-output circuit 512 via the dummy-clock-control circuit 510 and the dummy-signal-line delay 511. The dummy-output circuit 512 emulates the output circuit 505. A clock signal output from the dummy-output circuit 512 is supplied as a dummy-clock signal d-i-clk to the phase comparator 507 via the dummy-load circuit 513 and the dummy-input circuit 514. Here, the dummy-load circuit 513 emulates the output load of the output circuit 505, and the dummy-input circuit 514 has the same delay characteristics as the input circuit 501.
The phase comparator 507 makes a comparison of the reference-clock signal c-clk with the dummy-clock signal d-i-clk in terms of their phases. To ensure that both clock signals have the same phase, the phase comparator 507 controls the delay amount of the variable-delay circuit 509 via the delay-control circuit 508. In this manner, the clock signal output from the dummy-output circuit 512 is adjusted so as to have a predetermined timing relation with the input clock signal CLK.
A total delay of the variable-delay circuit 502, the clock-control circuit 503, the signal-line delay 504, and the output circuit 505 is equal to a total delay of the variable-delay circuit 509, the dummy-clock-control circuit 510, the dummy-signal-line delay 511, and the dummy-output circuit 512. Further, the internal-clock signal i-clk has the same phase as the dummy-clock signal d-clk. Because of this, when the clock signal output from the dummy-output circuit 512 has the predetermined timing relation with the input clock signal CLK, the data DQ output from the output circuit 505 ends up having the same predetermined timing relation with the input clock signal CLK.
When rising edges of the reference-clock signal c-clk are delayed behind corresponding rising edges of the dummy-clock signal d-clk by one cycle of the clock signal CLK, for example, rising edges of the clock signal output from the dummy-output circuit 512 will have the same timing as rising edges of the clock signal CLK. FIG. 2 is a timing chart showing the case in which the rising edges of the clock signal output from the dummy-output circuit 512 has the same timing as the rising edges of the clock signal CLK. In this case, the data DQ is output in synchronism with the rising edges of the clock signal CLK.
In this configuration, even when the characteristics of the input circuit 501, the variable-delay circuit 502, the clock-control circuit 503, the signal-line delay 504, and the output circuit 505 are changed due to variations in a power voltage and/or temperature, the characteristics of the dummy-input circuit 514, the variable-delay circuit 509, the dummy-clock-control circuit 510, the dummy-signal-line delay 511, and the dummy-output circuit 512 also change in the same manner. Because of this, the data DQ output from the output circuit 505 to the exterior of the device always keeps the same timing relation with the input clock signal CLK regardless of a power-voltage variation and/or a temperature variation.
The delay-control circuit 508 detects setting of a delay to a maximum delay when the delay-control circuit 508 is set to the maximum delay. The variable-delay circuits 502 and 509 controlled by the delay-control circuit 508 is comprised of a predetermined number of delay elements connected in series, and there is inevitably a limit to the maximum number of delay elements which can be used. When an attempt is made to increase a delay amount beyond this limit, such an attempt is bound to fail. In this case, the overflow detector 515 generates an overflow signal based on a maximum-delay-detection signal supplied from the delay-control circuit 508. The overflow signal is provided to the clock-control circuit 503.
The clock-control circuit 503 when the overflow signal is supplied selects the internal-clock signal i-clk having bypassed the variable-delay circuit 502 rather than a delayed-clock signal dll-clk supplied from the variable-delay circuit 502. The clock-control circuit 503 then supplies the internal-clock signal i-clk to the output circuit 505 via the signal-line delay 504.
In the configuration of FIG. 1, the reference-clock signal c-clk preferably has a phase thereof adjusted to a predetermined phase relation with the phase of the internal-clock signal i-clk, such that the data DQ from the output circuit 505 is output at a timing delayed behind the rising edges of the clock signal CLK by 1+m (m&lt;1) cycles. When a cycle of the clock signal CLK is 10 ns with m being 1/4, for example, the data DQ is output 12.5 ns (2.5 ns on appearance) after a rising edge of the clock signal CLK. When the cycle of the clock signal CLK is extended to 20 ns, for example, the data DQ is output 25 ns (5 ns on appearance) after a rising edge of the clock signal CLK.
When the clock signal CLK has a relatively long cycle as in the latter example, the delayed-clock signal dll-clk from the variable-delay circuit 502 may have a phase which is delayed behind the internal-clock signal i-clk by more than one clock cycle. In such a case, the internal-clock signal i-clk, rather than the delayed-clock signal dll-clk, is selected by the clock-control circuit 503 so as to output the data DQ at a timing based on the internal-clock signal i-clk. By doing so, the data DQ can be output with a delay of 3 ns, for example. Since it is preferable to access the data DQ as early as possible, use of the internal-clock signal i-clk for outputting the data is a desirable measure to be taken when the clock signal CLK has a relatively long cycle.
Where the internal-clock signal i-clk is selected as the delayed-clock signal dll-clk is delayed behind the internal-clock signal i-clk by more than one cycle, excessive consumption of power is resulted. This is because the DLL circuit unduly continues its operations despite the fact that the internal-clock signal i-clk is used for outputting the data DQ.
Further, the continuing operations of the DLL circuit results in the delay amount of the variable-delay circuits 502 and 509 being increased without a justifiable need. In this case, the delay amount needs to be decreased one stage by one stage when a clock signal of a shorter cycle is used in a subsequent operation. This means that an excessively large number of cycles will be necessary before the DLL circuit locks on.
Accordingly, there is a need for a semiconductor device equipped with a DLL circuit which can reduce excessive power consumption, and shorten a time period required for achieving a lock-on condition when a clock signal switches from a longer cycle to a shorter cycle.